`timescale 1ns /100ps

`include "tag.v"
`include "data.v"

module cacheins(clk,adr,SysFe_data,linia_mem,ready,rst,fisica,dataOut,hit);
	input [6:0] adr;
	input [63:0] SysFe_data;
	input [2:0] linia_mem;
	input ready, rst, clk;
	input [4:0]	fisica;		
	
	output [15:0] dataOut;
	output hit;
	
	wire [6:0] tagOut;
	wire [63:0] dataOut0;
	wire [1:0] error;
	
	reg [15:0] dataOut;
	reg [1:0] size;
	reg [2:0] bt;
	reg hit;
	reg we;
	
	tags etiquetes(clk, rst ,{fisica,1'b1,1'b0}, tagOut, we, adr);
	
	data dades(SysFe_data, dataOut0, clk, we, adr, size, bt, error);
	
	initial	
		begin
			we = 0;
			size = 2'b10;
			bt = 3'b0;
		end
	
	always @(negedge clk)
		begin
			if(ready == 1)
				begin
					we = 1;
					size = 2'b00;
					bt = 3'b0;
				end
			else
				begin
					we = 0;
					size = 2'b10;
					bt = linia_mem;
				end
			if((fisica == tagOut[6:2]) && (tagOut[1] == 1))
				begin
					hit = 1;
					dataOut = dataOut0[15:0];  
				end
			else 
				hit = 0;
		end 
	
endmodule